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S E M I C O N D U C T O R, I N C .
TQ8213
The TQ8213 is a SONET/SDH OC48 MUX that time-division multiplexes a 16-bit or 32-bit parallel data bus to a serial 2.48832 Gb/s NRZ data stream for transmission through a communications channel. Without any additional amplification, the 2.48832 Gb/s output stage can drive either a directly modulated laser or an optical external modulator. Output may also be configured to provide standard ECL/PECL levels with excellent rise/fall times. The serial output data stream is available through either singleended or differential pins. Mark/space ratio adjustment allows compensation for asymmetries encountered in optoelectronics. The TQ8213 operates in two different time-division multiplexing modes, making it extremely flexible for use in telecom and datacom applications. The serial 2.48832 Gb/s data stream can be generated from either a 16-bit wide 155.52 MHz data stream or a 32-bit wide 77.76 MHz data stream. Data integrity may be ensured through a byte-wise parity check, which occurs in parallel with the incoming data stream. An external parity alarm is set whenever a parity check error is detected. Transmit clocking is selectable from either an internal or external Voltage Controlled Oscillator(VCO) as well as a selectable external or internal Phase Locked Loop (PLL). The selected clock source may be monitored at HCKOUT. The internal PLL utilizes an external reference clock, REFCLK, to aid in timing generation. The reference clock may be one of seven commonly used system frequencies. A TTL level LOCK signal is supplied to indicate when the phase difference between the external reference clock and the internal divided down clock is less than /4 radians. Operating from a single +5V supply, the TQ8213 will provide fully compliant functionality and performance. Direct-connected TTL levels are used with both of the input modes. The TQ8213 is fully compliant with SONET/SDH jitter specifications.
PRELIMINARY DATA SHEET
OC48/STM16 Multiplexer
Features
* Single-chip 16:1 or 32:1 Multiplexer with integrated clocksynthesis and high performance 75mA/3.75V output driver * Output can drive external optical modulator, 50 PECL/ECL transmission line, or directly modulated laser without further amplification * Output symmetry adjust * Selectable internal/external active highspeed 2.48832 GHz clock * SONET/SDH compliant for 2.48832 Gb/s output data rate * 622.08, 311.04, 155.52, 77.76, 51.84, 38.88, or 19.44 MHz PECL or TTL reference clock inputs * Integrated PLL with external filter * Four output clocks at 311.04, 155.52, 77.76, and 38.88 MHz. * Internal even/odd (mode programmable) parity checker with alarm output * 23mm 208-pin BGA package * 5V single supply * -40 to +125C case operating temperature
1
TELECOM PRODUCTS
TQ8213
PRELIMINARY DATA SHEET
Figure 1. TQ8213 Block Diagram TDPERR
PARALM PARSEL RESET VDRIVE VSEN1
32
TD1(0:7)TD4(0:7) TDPAR(1:4)
TTL Buffer
Retime MUX
DOUT NDOUT VSEN10
4
MODE(0) MODE(1) VSYMX VLEVEL
Internal VSYMX Source
Internal VLEVEL Source
REFCLK REFCLKT
Phase Freq. Detector
Charge Pump
VTUNEO
LOCK
CK311 REFSEL0 REFSEL1 REFSEL2 VOSC VTUNEIN CLKIN NCLKIN CLKSEL
VCO 1 0 Clock Input Selector
2.48832GHz Active Clock
CK155
Clock Divider
CK78 CK39
50 Resistive Tap
HCKOUT
2
TQ8213
PRELIMINARY DATA SHEET
Timing Generation The TQ8213 utilizes an external 2.48832 GHz (nominal) reference clock, or generates a 2.48832 Ghz clock through an internal VCO. The active clock can be monitored on a 50 output, HCKOUT. The active clock is selected via the CLKSEL pin as shown in the following table. CLKSEL N.C. VEE Active Clock External Clock (CLKIN) Internal VCO
REFSEL2 0 0 0 0 1 1 1
REFSEL1 0 0 1 1 0 1 1
REFSEL0 0 1 0 1 1 0 1
REFCLK Freq. 19.44 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.02 MHz 311.04 MHz 622.08 MHz
External Clock VCO and PLL The external clock, CLKIN and NCLKIN, may be input as either single-ended (unused input must be externally terminated through a capacitor to an AC ground) or differential and must be AC coupled. The external clock is selected as the active clock if the CLKSEL line is left open(N.C.). Note VOSC and VTUNEIN must be tied to VEE when using an external VCO. Internal Clock VCO and PLL
The PFD compares the phase between an internal clock divided from the active clock and the reference clock at REFCLK. The PFD's phase error signals are then integrated by the Charge Pump and external loop filter, which provides a VCO tune voltage at VTUNEO. See Table 4 for recommended external loop filter passive values. The internal PLL is completed by connecting VTUNEO to VTUNEIN. The internal PLL provides an active high TTL in-lock indicator at LOCK when the phase difference between external reference clock and the internal divided down clock is less than /4 radians. Internal Clock and VCO and External PLL
See Figure 8 for operation with the internal clock and PLL. The internal clock is selected when CLKSEL is tied to VEE and the external power supply pin, VOSC, is tied to VDD. CLKIN must be tied to VEE through a 10k resistor when the internal clock is used. The internal PLL is composed of a Phase/Frequency Detector (PFD), a charge pump, and the internal VCO. An external system reference clock must be provided at REFCLK (PECL) or REFCLKT (TTL). The unused REFCLK or REFCLKT input must be tied to a logic low. The reference clock can be one of seven different frequencies. Control pins, REFSEL2, REFSEL1, and REFSEL0, are set according to the following table when the corresponding reference clock frequency is used.
See Figure 9 for operation with the internal clock and external PLL. When an external PLL is used an internally generated clock (such as CK39) and VTUNEIN can be used in the external PLL. Output Clocks The TQ8213 contains an internal Clock Divider block which frequency divides the active clock (internal or external source as selected by the CLKSEL). The Clock Divider supplies the internal clock signals necessary for the re-timing and multiplexing functions. The Clock Divider block also outputs four external clocks: a 311.04 MHz differential PECL clock at CK311 and NCK311, a 155.52 MHz PECL clock at CK155, a 77.76
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TELECOM PRODUCTS
SONET/SDH/ATM PRODUCTS
Function Description
TQ8213
PRELIMINARY DATA SHEET
Functional Description (continued)
MHz TTL clock at CK78, and a 38.88MHz PECL clock at CK39. Note that the above clock frequencies are dependant upon using the part at 2.48832 GHz. Data Multiplexing and Parity Checking The TQ8213 can be configured to run in one of two modes. The demultiplexing modes are set by fixing the MODE(1) and MODE(0) package pins according to the following table. MODE(1) MODE(0) N.C. VEE VEE N.C. VEE VEE Multiplexing Mode 16:1 32:1 TBD is then 16:1 multiplexed inside the MUX block. See Figure 5. For 32:1 multiplexing applications, the TQ8212 receives a 32-bit wide 77.76 MHz data bus at the TD1(0:7), TD2(0:7), TD3(0:7), TD4(0:7) pins, and four 77.76 MHz parity bits at the TDPAR1, TDPAR2, TDPAR3, and TDPAR4 pins. The 32-bit wide data and parity bits are re-timed by an internal 77.76 MHz clock which is supplied from the Clock Divider block. Incoming data integrity is ensured by a byte-wise parity check performed internally on the re-timed TD1(0:7), TD2(0:7), TD3(0:7), TD4(0:7) data with the respective re-timed TDPAR1, TDPAR2, TDPAR3, and TDPAR4 parity bits. The multiplexer will function properly if the parity is not used or is incorrect. An active high PECL parity alarm flag, PARALM, and an active low TTL alarm flag, TDPERR, are generated and held for a minimum of 25ns when a parity error is detected. The re-timed 32-bit wide 77.76 MHz data bus is then 32:1 multiplexed inside the MUX block. See Figure 6. 2.5Gb/s Output Driver The TQ8213 has a high power output stage to provide an output level suitable for directly driving a 3.75V modulator or 75mA laser. The separate power supply pin for the output stage is VDRIVE. When VDRIVE is 8.3V the back terminated output driver swing can be between 0.5-3.75V. This corresponds to 10-75mA into a 50 forward load. The amplified 2.48832 Gb/s data stream is available as a differential or single ended signal at DOUT and NDOUT. The data amplitude may be adjusted using VLEVEL and the crossing level of the output data eye can be adjusted using VSYMX. Both of these levels are preset internally to 1.88V and a 50%duty cycle if VLEVEL and VSYMX are left open (N.C.).
Parity mode is programmable by PARSEL. If PARSEL is left open, the TQ8213 checks for even parity. If PARSEL is tied to VEE, the TQ8213 checks for odd parity. For all modes the first output bit in time is TD10. The remainder of the data is output sequentially from TD11 through TD27. The most significant byte is Byte #1 which is TD10 through TD17. For 16:1 multiplexing applications, the TQ8212 receives an 16-bit wide 155.52 MHz data bus at the TD1(0:7) and TD2(0:7) pins, and two 155.52MHz parity bits at the TDPAR1 and TDPAR2 pins. The 16-bit wide data and parity bits are re-timed by an internal 155.52 MHz clock supplied by the Clock Divider Block. Incoming data integrity is ensured by a byte-wise parity check performed internally on the re-timed TD1(0:7) and TD2(0:7) data with the respective re-timed TDPAR1 and TDPAR2 parity bits. The multiplexer will function properly if the parity is not used or is incorrect. An active high PECL parity alarm flag, PARALM, and an active low TTL alarm flag, TDPERR, are generated and held for a minimum of 25ns when a parity error is detected. The re-timed 16-bit wide 155.52MHz data bus
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TQ8213
PRELIMINARY DATA SHEET
The output current level and voltage amplitude at DOUT and NDOUT can be set using an external feedback control loop. To set the output current level, connect an external current source, Isource, equal to 10% of the desired output, to VSEN10. Connect VLEVEL, VSEN10 and VSEN1 to an amplifier, as shown in Figure 2, with a minimum input common mode range of (Isource*50). The choice of the external current source also sets the output voltage swing. For example, to achieve the maximum swing of 3.75V into 25 (50 internal back-terminated impedance in parallel with a 50 forward load), a 15mA source must be used (Isource*10*25 =150mA*25 = 3.75V).
FIgure 2 Output Level Control
5V-10V VDRIVE
50
50
DOUT NDOUT
Pre Amp
VLEVEL VSEN1 Isource
5
50
VSEN10 3mA - 15mA
VEE 0V
5
TELECOM PRODUCTS
SONET/SDH/ATM PRODUCTS
TQ8213
PRELIMINARY DATA SHEET
Figure 3. TQ8213 Pinout -Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A B C D E F G H J K L M N P R T U
VEE CLKIN VSEN10 VSEN1 NDOUT DOUT VDD MODE0 MODE1 VEE NCLKIN VEE VDRIVE VDRIVE VDD VSYMX VEE
VDD
VDD
VDD
VEE
VDRIVE
VDRIVE
VDD
RESET
VDD
VDD
VDD
VEE
TD4(7)
VEE
VDD
VDD
VDD
VEE
VLEVEL
VDRIVE VDRIVE
VDD
VEE
VDD
VDD
VEE
TD4(4)
TD4(5)
VEE
PARALM REFSEL2 TDPERR
TD4(2)
TD4(3)
TD4(6)
VDD
REFSEL1 REFSEL0 LOCK
CLKSEL
TD4(0)
TD4(1)
VDD
VDD
TQ8213
208-pin BGA Top View
VDD VDD VDD TDPAR1 TD1(7) TD1(0) VEE
VDD
VDD
VEE
VEE
VDD
PLLVDD
PLLVEE
TDPAR4 TDPAR3
TD3(7)
VOSC
VEE
TD3(6)
TD3(5)
TD3(4)
VEE
VEE
VDD
VTUNEIN
VDD
TD3(0)
VDD
VDD
VEE
VTUNEO
TD3(3)
VEE
VDD
VDD
CK78
VEE
HCKOUT
TD3(2)
VEE
VDD
VDD
CK39
CK155
NCK311
TD3(1)
VEE
VDD
VDD
VDD
PARSEL
VEE
CK311
VDD
VEE
VDD
TD2(5)
TD2(3)
VDD
TDPAR2
TD1(6)
TD1(1)
VEE
VEE
VDD
VEE
REFCLKT
VEE
TD2(6)
TD2(1)
VEE
TD1(5)
VEE
TD1(2)
VEE
VEE
REFCLK
VEE
TD2(7)
TD2(4)
TD2(2)
TD2(0)
TD1(4)
TD1(3)
VDD
ID
A B C D E F G H J K L M N P R T U
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
= NC (Do Not Connect)
Note: Heat Spreader is at VDD volts.
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TQ8213
PRELIMINARY DATA SHEET
Pin No. 17 16
Grid Ref. Signal A14 A15
Type and Freq. or Bit Rate
Description MODE(1) = N.C., MODE(0) = N.C. = 8:1 multiplexing MODE(1) = N.C., MODE(0) = VEE = 16:1 multiplexing MODE(1) = VEE, MODE(0) = N.C. = 32:1 multiplexing Byte #1, Most significant byte. Byte wide 155.52 MHz, or 77.76 MHz input data. TD1(0) is the MSb Mux input data bit. Mux input data bit. Mux input data bit. Mux input data bit. Mux input data bit. Mux input data bit. Byte 1 Mux input data bit. TD1(7) is the least significant bit. Parity bit signal for the byte wide data at TD1(0) to TD1(7). The parity bit is defined to be in parallel with the byte wide data at TD1(0) to TD1(7) from which it was calculated. Byte #2 Byte wide 155.52 MHz or 77.76 MHz Mux input data. TD2(0) is the most significant bit. Mux input data bit. Mux input data bit. Mux input data bit. Mux input data bit. Mux input data bit. Mux input data bit. Byte 2 Mux input data bit. TD2(7) is LSb Parity bit signal for the byte wide data at TD2(0) to TD2(7). The parity bit is defined to be in parallel with the byte wide data at TD2(0) to TD2(7) from which it was calculated. Byte #3 Byte wide 77.76Mb/s input data. TD3(0) is the MSb. Mux input data bit. Mux input data bit. Mux input data bit. Mux input data bit. Mux input data bit. Mux input data bit. Byte 3 Mux input data bit. TD3(7) is the least significant bit.
Data Multiplexing Configuration
MODE(0) TTL MODE(1) TTL
155.52 MHz, 77.76 MHz
141 140 139 138 134 132 135 136 131 P11 R11 T11 U11 U10 T9 R10 P10 P9 TD1(0) TD1(1) TD1(2) TD1(3) TD1(4) TD1(5) TD1(6) TD1(7) TDPAR1 Input TTL 155.52 MHz, 77.76 MHz Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL
125
U7
TD2(0)
Input TTL 155.52 MHz or 77.76 MHz Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL
124 123 122 119 118 117 116 130
T7 U6 R7 U5 R6 T5 U4 R9
TD2(1) TD2(2) TD2(3) TD2(4) TD2(5) TD2(6) TD2(7) TDPAR2
77.76 MHz Interface
90 89 88 87 84 83 82 81 L2 P1 N1 M1 K3 K2 K1 J3 TD3(0) TD3(1) TD3(2) TD3(3) TD3(4) TD3(5) TD3(6) TD3(7) Input TTL 77.76Mb/s Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL
7
TELECOM PRODUCTS
SONET/SDH/ATM PRODUCTS
Table 1. Signal Description
TQ8213
PRELIMINARY DATA SHEET
Table 1. Signal Description (continued)
Pin No. 79 Grid Ref. Signal J2 TDPAR3 Type and Freq. or Bit Rate TTL Description Parity bit signal for the byte wide data at TD3(0) to TD3(7). The parity bit is defined to be in parallel with the byte wide data at TD3(0) to TD3(7) from which it was calculated. Byte #4 Byte wide 77.76Mb/s input data. TD4(0) is the most significant bit. Mux input data bit. Mux input data bit. Mux input data bit. Mux input data bit. Mux input data bit. Mux input data bit. Byte 4 Mux input data bit. TD4(7) is the least significant bit. Parity bit signal for the byte wide data at TD4(0) to TD4(7). The parity bit is defined to be in parallel with the byte wide data at TD4(0) to TD4(7) from which it was calculated. 311.04 MHz clock output. Must be externally terminated by RTe to VTTe. Complement of CK311. Must be externally terminated by RTe to VTTe. 155.52 MHz clock output. Must be externally terminated by RTe to VTTe. 77.76 MHz clock output. 38.88 MHz clock output. Must be externally terminated by RTe to VTTe. Parity alarm flag. Active low TTL logic signal indicating the detection of a parity error. Remains low for at least 25 ns when active. Parity alarm flag. Active high PECL logic signal indicating the detection of a parity error. Remains high for at least 25 ns when active. Must be externally terminated by RTe to VTTe. High speed differential data output. DOUT is true output. Must be AC coupled. Complement of DOUT. Must be AC coupled. Rise/fall time symmetry adjust control signal input. Input impedance is typically 10 k. Output data amplitude adjustment control signal input. Input impedance is typically 10 k. Power supply input for high power output stage, nominally at (VDD+3.3 V) or VDD.
73
G1
TD4(0)
Input TTL 77.76Mb/s
72 71 70 67 66 65 64 78
G2 F1 F2 E1 E2 F3 D1 J1
TD4(1) TD4(2) TD4(3) TD4(4) TD4(5) TD4(6) TD4(7) TDPAR4
Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL Input TTL
170 171 169 168 167 201
P17 N17 N16 M15 N15 E17
CK311 NCK311 CK155 CK78 CK39 TDPERR
Output PECL 311.04 MHz Output PECL 311.04MHz Output PECL 155.52 MHz Output TTL 77.76 MHz Output PECL 38.88 MHz Output TTL 38.88 MHz
200
E15
PARALM Ouput PECL 38.88 MHz
2.5Gb/s Output Interface
29 30 22 38 A9 A8 B11 D7 DOUT NDOUT VSYMX VLEVEL (Note 2) Output AC 2.48832 Gb/s Output AC 2.48832Gb/s Input Analog DC (Note 2) Input Analog DC Power rail DC
26,27,28 B9,C9,D9 VDRIVE 31,32,33 B8,C8,D8
8
TQ8213
PRELIMINARY DATA SHEET
Pin No. 34 37
Grid Ref. Signal A7 A6 VSEN1 VSEN10
Type and Freq. or Bit Rate Output Analog DC I/O Analog DC
Description Output current level sensing pin. VSEN1 voltage is directly proportional to the output current level at DOUT and NDOUT. Output current level reference pin. When driven with an external current source at exactly 1/10 the output current level on DOUT and NDOUT, the voltage at VSEN10 is the equal to VSEN1. Power supply for the internal VCO. VDD = VCO ON; VEE = VCO OFF Frequency tuning voltage for the internal VCO. Negative tune slope. Must be tied to VEE when using an external VCO. High frequency clock input. Must be AC coupled. The signal must be externally terminated by RTe to VTTe. The clock reference level is derived from VTTe. Must be externally terminated by 10k to VEE when internal VCO is used. Complement of CLKIN High speed clock monitor tap. 60mVpp with a 50. load. Clock select signal for choosing between external or internal clock source as the active clock. NC = External Clock Source; VEE = Internal VCO Reference clock input to internal phase/frequency detector. Values at REFSEL(0:2) must correspond to the reference clock frequency being used. This signal must be externally terminated by RTe to VTTe. When not in use tie to VTTe. Reference clock input to internal phase/frequency detector. Values at REFSEL(0:2) must correspond to the reference clock frequency being used. When not in use tie to VEE. Reference Clock Frequency Select (REFSEL0 = REFSEL1 = REFSEL2 = VEE) (REFSEL0 = VDD, REFSEL1 = REFSEL2 = VEE) (REFSEL0 = REFSEL2 = VEE, REFSEL1 = VDD) (REFSEL0 = REFSEL1 = VDD, REFSEL2 = VEE) (REFSEL0=VDD,REFSEL1=VEE,REFSEL2=VDD) (REFSEL0 = VEE, REFSEL1 = REFSEL2 = VDD) (REFSEL0 = REFSEL1 = REFSEL2 = VDD) 19.44 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.02MHz 311.04 MHz 622.08 MHz
Phase-Locked Loop Elements
182 181 50 J14 K17 A3 VOSC Power rail DC
VTUNEIN Input Analog CLKIN Input AC 2.48832 GHz
49 176 199
B3 M17 F17
NCLKIN HCKOUT CLKSEL
Input AC 2.48832 GHz Output AC 2.48832 GHz TTL
164
T17
REFCLK
Input PECL Reference Clock
165
R17
REFCLKT Input TTL Reference Clock
196 197 198
F15 F14 E16
REFSEL0 TTL REFSEL1 TTL REFSEL2 TTL
180
L17
VTUNEO
Output Analog
Internal PLL charge pump loop filter output. Connection for external components for the internal PLL charge pump loop filter and to VCO tune input. Internal PLL lock detector. Signal is high when PLL in lock.
194
F16
LOCK
Output TTL
9
TELECOM PRODUCTS
SONET/SDH/ATM PRODUCTS
Table 1. Signal Description (continued)
TQ8213
PRELIMINARY DATA SHEET
Table 1. Signal Description (continued)
Pin No. 14 160 Grid Ref. Signal C11 P15 RESET PARSEL Type and Freq. or Bit Rate Input PECL Input TTL Description Chip reset (active low). When not used must be tied to VDD through RTe When PARSEL=NC a byte-wise even parity check is performed. When PARSEL=VEE a byte-wise odd parity check is performed Part level identification. Voltage at ID indicates device type. PLL positive supply voltage. PLL supply return. Pin Number,Grid Reference 9,D12 54,C3 103,P4 99,R2 178,K15 206,D14 101,N3 150,R13 175,L16 51,A2 177,K14 3,B17 12,B12 44,C5 95,R1 185,J17 202,D17 149,T14 75,H3 129,U8 25,A10 55,D3 104,P3 158,R15 192,G14 145,U14 102,P2 153,P13 193,G16 52,B2 184,J16 4,A16 13,C12 45,A4 96,M2 186,H17 203,E14 144,U13 98,N2 143,T12 24,B10 53,D4 109,P5 157,P14 191,G15 100,N4 105,R3 154,R14 1,B16 60,D2 205,D16 5,D13 18,A13 46,B4 107,U1 151,U15 204,D15 39,A5 77,H1 179,K16 21,C10 62,F4 113,R5 161,N14 207,C15 86,L1 106,T2 155,T15 2,C17 61,E3 15,D11 7,B15 19,A12 56,A1 108,U2 152,U16 121,T6 147,R12 91,L4 20,D10 68,G4 114,P6 166,M14 208,C16 69,G3 112,U3 156,T16 35,B7 76,H2 162,R16 8,C13 23,A11 57,E4 110,R4 189,H16 133,U9 146,P12 63,C1 42,C6 74,H4 120,P7 172,L14 6,C14 128,T8 163,P16 36,C7 85,K4 10,B14 40,B6 58,B1 111,T3 183,J15 142,U12 97,T1 80,J4 48,D5 94,M4 127,R8 173,L15 47,C4 137,T10 174,M16 43,D6 93,M3 11,B13 41,B5 59,C2 115,T4 195,G17 148,T13 92,L3 126,P8
Power Pins and Spare Pins
159 187 188 Signal VDD
U17 H14 H15
ID PLLVDD PLLVEE
Output Analog Input DC
Description Positive rail supply voltage
VEE
Negative rail supply voltage
NC
DO NOT CONNECT
Notes:
1.Symbol definitions: NC refers to a no-connect signal. Do Not Connect these pins! ECL refers to an Emitter Coupled Logic signal PECL refers to a Positive ECL TTL refers to a Transistor-Transistor Logic signal AC refers to AC coupled signal 2. This signal is internally generated and can be overdriven externally.
10
TQ8213
PRELIMINARY DATA SHEET
Parameter Supply voltage Internal VCO Supply voltage Output stage supply voltage Inputs/Outputs Tstg, Storage Temperature
Symbol VDD-VEE VOSC VDRIVE
Min 0 VEE-0.5 VDD-0.5 VEE-0.5 -55
Max 7 VDD+0.5 VDD+5.0 VDD+0.5 150 125 150 1000
Unit V V V
oC oC oC
Tc, Maximum Case Operating Temperature Tj, Maximum junction temperature Electrostatic Discharge (100 pF, 1.5 k)
V
Notes: 1. The internal VCO specification applies when Tc is within operating range. The internal VCO is operational down to -20o
Table 3. DC Operating Ranges
Signal VDD-VEE (Note 1) VOSC (Note 1) PLLVDD-PLLVEE (Note 1) VDRIVE (Note 1) Symbol VDD-VEE Vosc Iosc PVDD-PVEE IPLL Vdrive Idrive Tc Parameter Supply voltage range Internal VCO supply Supply current for internal VCO PLL supply voltage Supply current for internal VCO Output stage power supply Supply current for output stage Case temperature measured at the case Min 4.75 +5.0 -40 Typ 5.00 VDD 14 VDD +10 Max 5.25 40 +10.5 150 125 Units V V mA V mA V mA oC
Notes:
1. 2.
No special power up sequence is required. VEE at operating range.
Table 4. Power Dissipation
Low Speed Outputs Open Open Open Open Open Open Open Open Fully Loaded Driver Mod Current (mA) 0 0 20 (Note 1) 20 60 60 75 75 0 VDD (V) 5.0 5.25 5.0 5.25 5.0 5.25 5.0 5.25 5.0 VDRIVE (V) 5.0 5.25 5.0 5.0 6.75 6.75 10.5 10.5 4.72 Typ Power (W) Max Power (W) 3.33 4.06 3.51 4.24 3.96 4.69 4.62 5.35 3.53
Notes: 1. Using a Lucent D-372 laser with 20 mA of modulation current will generate 3 dBm of optical power.
11
TELECOM PRODUCTS
V
SONET/SDH/ATM PRODUCTS
Table 2. Absolute Maximum Ratings
TQ8213
PRELIMINARY DATA SHEET
Table 4. Recommended External Loop Filter Values (for 500MHz/V KVCO)
REFCLK Frequency (MHz)
19.44 38.88 51.84 77.76 155.52 311.04 622.08
Resistor Value R1 ()
2.2k 1.2k 910 600 600 600 600
Capacitor Value C1 (F)
0.1 0.1 0.1 0.1 0.1 0.1 0.1
Capacitor Value C2 (pF)
5.1 8.6 11.2 17 17 17 17
VTUNEO C1 C2 R1
PLLVDD
Table 6. VCO Control Signal Specifications
Signal VTUNEO Symbol Vrange KVCO frange Parameter VTUNEO voltage range (Note 1) VCO VTUNE voltage gain VCO frequency range when using internal PLL Min Typ 2.5 500 1950 - 2700 Max Units V MHz/V MHz
Notes:
1. A VTUNEO voltage of 2.5V corresponds to approximatey a 2.5GHz center frequency.
Table 7. Driver Control Signal Specifications
Signal VSYMX Symbol Vsymx Asymx Vdef Zsymx Vlevel Aamp Zlevel Rsen1 Isen1 Rsen10 Isen10 Parameter VSYMX overdrive voltage linear range Output data crossing level adjust gain Default output level (Note 1) VSYMX input impedance VLEVEL overdrive voltage linear range Output data amplitude adjust gain VLEVEL input impedance VSEN1 equivalent resistance VSEN1 input current range VSEN10 equivalent resistance VSEN10 input current range Min Vdef-1 Typ Vdef 15 1.88 10 1.6 10 5 50 Max Vdef+1 Units V %/V V k V V/V k mA mA
VLEVEL
0.5
2.5
VSEN1 VSEN10
4.5 20 45 2
5.5 150 55 15
12
TQ8213
PRELIMINARY DATA SHEET
Signal CLKIN NCKLIN DOUT NDOUT (Note 2)
Symbol tcki tckdc Vpp Tpw Trise Tfall Jpp Vmean_max Vmean_min Xingmin Xingmax DXing %over %under %ripple
Description Input clock period Input clock duty cycle (Note 1) Input clock peak-to-peak voltage Output data pulse width Output data rise time Output data fall time Output data peak-peak jitter (Note 3) Output data mean pk-pk for high output applications; Vdrive = +10 V Output data mean pk-pk for high output applications; Vdrive = +5 V Min. data crossing level adjustment range with VSYMX at 1.38 Max. data crossing level adjustment range with VSYMX at 2.38 Absolute variation in output data crossing level over full VLEVEL operating range Overshoot Undershoot Ripple High speed output clock period High speed output clock peak-to-peak voltage High speed output clock output impedance
Min
Nom
Max
Units % mV % ps ps ps V V
370.4 ps 401.88 ps 250 ns 40 50 60 1000 1200 1400 95 100 8 3.75 0.5 30 60 -5 10 45 35 65 401.88 50 40 70 +5 10 10 10 55 105 130 130 20
% % % % % % ps mV
HCKOUT
thcko Vpp RTe
Notes:
1.Defined as percentage of the input clock period. Duty cycle is measured at the average voltage of the signal. 2.Refer to Figure 9. All specifications for output data apply under the following conditions: Output Data Pattern: 223-1 PRBS, 2.48832 Gbit/s DOUT and NDOUT termination: 50 to VEE Termination network return loss: >20 dB, 0 to 1 GHz >10 dB, 1 to 3 GHz >6 dB, 3 to 5 GHz Vlevel: over specified operating range VSYMX: adjusted to give 50% data crossing 3.Specified as the peak to peak jitter shown in Figure 9. This specification does not include the reference clock and measurement system jitter. This is accomplished by first measuring the peak-to-peak jitter of the reference clock and subtracting this value from the measured peak-to-peak jitter for the device under test using the same measurement system.
Table 9. Jitter Transfer Performance
Symbol Jpeaking fc Description Peak Gain in Transfer Curve Corner Frequency Transfer Curve Nom 0.02 1.54 Max 0.1 2.0 Units dB MHz
Note: Jitter Transfer measurments were performed with the PLL loop filter values specified in Table 5. The method used is outlined in a Jitter Bench application note available upon request. The values listed as nominal were performed under the following conditions: DOUT = 3.5 Vp-p VDD = 5 V Tcase = 60 C
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Table 8. 2.5GHz and 2.5Gb/s High Speed Signal Specifications
TQ8213
PRELIMINARY DATA SHEET
Figure 4. Typical Jitter Transfer Curve (REFCLK = 77.76 MHz)
0
-5
-10
Gain (dB)
-15
Transfer, 5.0V, 50C SONET/SDH Template
-20
-25
-30
-35
-40 1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Frequency (Hz)
Table 10. Jitter Generation Performance
Jitter Generation JPP JRMS Nom 6.0 1.0 Max 20 2.0 Units ps ps
Note: Jitter Generation measurments were performed with the PLL loop filter values specified in Table 5. The method used is outlined in a Jitter Bench application note available upon request. The values listed as nominal were performed under the following conditions: Data Rate = 2.48832 Gb/s DOUT = 3.5 Vp-p VDD = 5 V Tcase = 60 C
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TQ8213
PRELIMINARY DATA SHEET
Signal CK311 NCK311 CK155 CK39 (Note 1) RESET REFCLK
Symbol tckdc tckr tckf Voh Vol Vamp trf Vih Vil
Description Output clock duty cycle (Note 2) Output clock rise time (20% to 80%) Output clock fall time (20% to 80%) Output clock high level Output clock low level Output clock amplitude (Note 3) Reset fall time (20% to 80%) Input high level Input low level Output high level Output low level
Min 40
Nom 50
Max 60 750 750 VDD-0.6 VDD-1.6
Units % ps ps V V mV
VDD-1.05 VTTe VDD-1.0 VTTe
300 ps VDD-0.4 V VDD-1.55 V VDD-0.6 VDD-1.6 V V
PARALM Voh Vol
Notes:
1. All specifications apply with CK311 CK155 and CK39 terminated with RTe to VTTe. 2.Output clock duty cycle is measured at the mean voltage of the signal and nominal input clock frequency of 2.48832GHz. 3.The CK311, CK155 and CK39 clock output amplitude is measured with respect to the mean voltage of the signal.
Table 12. TTL Interface Specifications
Signal CK78 LOCK TDPERR (Note 2) Symbol tckdc tckr tckf Voh Vol Cload Tsu Tho Vih Vil Iih Iil Cin Description 78 MHz output clock duty cycle (Note 1) 78 MHz output clock rise time (20% to 80%) 78 MHz output clock fall time (20% to 80%) Logic output high level Logic output low level Output load capacitance Input data setup time (Note 2) Input data hold time (Note 2) Input data high voltage (Note 3) Input data low voltage (Note 3) Input data high-level input current Input data low-level input current Input data capacitance Logic input high level Logic input low level Min 40 Nom 50 Max 60 2000 2000 VDD 0.4 500 2500 VDD VEE+0.8 200 VDD 0.8 Units % ps ps V V pF ps ps V V uA uA pF V V
2.4 VEE 20
TD1(0:7)TD4(0:7) TDPAR1TDPAR4
VDD-3.0 VEE -400 2.0 VEE
-200 10
MODE(0:1)Vih PARSEL Vil REFSEL(0:2) REFCLKT
Notes:
1.Output clock duty cycle is measured at the mean voltage of the signal and nominal input clock frequency of 2.48832GHz. 2.The parity alarm flag TDPERR is an active LOW TTL signal. When a parity error is detected, TDPERR must remain active (logic LOW) for the minimum duration of 25 ns The occurrence of further parity errors during this hold time when TDPERR is active will be ignored. 3.Tsu and Tho are specified relative to the rising edge of CK78 and the falling edge of CK155. See Figure 5 and Figure 6. Input data edge jitter is not included in the specifications. The input data bus bits are assumed to be free of any skewing in time. The specifications apply under the following conditions: Input data rise/fall time: < 800ps (20% to 80%) Input data: 223-1 PRBS, 16x155 Mb/s or 32x77.76 Mb/s Output clock frequency: 155.52MHz or 311.04MHz Output CK155 termination: RTe to VTTe
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TELECOM PRODUCTS
VDD-1.0 VTTe +/-350
SONET/SDH/ATM PRODUCTS
Table 11. PECL Interface Specifications
TQ8213
PRELIMINARY DATA SHEET
Figure 5. AC Timing: 155.52 Mb/s
CK155 Tsu Tho
TD1(0:7) TD2(0:7)
Valid Data
Valid Data
Figure 6. AC Timing: 77.76 Mb/s
CK78 Tsu TD1(0:7) TD2(0:7) TD3(0:7) TD4(0:7) Tho
Valid Data
Valid Data
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TQ8213
PRELIMINARY DATA SHEET
CK311
CK155 TCK78 CK78
TCK39 CK39
Table 13. Output Clock Timing Relationships
Symbol Description CK311 to CK155 timing relation CK311 to CK78 timing relation CK311 to CK39 timing relation Typ 502 78 1800 Max Units pS pS pS
TCK155 TCK78 TCK39
Figure 8. Reference and Bus Clock Timing Relationship
REFCLK
TSKEW Bus Clock
Table 14. Reference and Bus Clock Timing Relationship
REFCLK 77.76 MHz TTL 77.76 MHz PECL 155.52 MHz TTL 155.52 MHz PECL Bus Clock CK78 CK78 CK155 CK155 Symbol Description Falling Edge Time Offset Falling Edge Time Offset Falling Edge Time Offset Falling Edge Time Offset Min 10.2 10.1 5.0 4.9 Typ 11.2 11.1 5.7 5.6 Max 12.5 12.3 6.7 6.5 Units nS nS nS nS
TSKEW TSKEW TSKEW TSKEW
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TELECOM PRODUCTS
TCK155
SONET/SDH/ATM PRODUCTS
Figure 7. Output Clock Timing Relationships
TQ8213
PRELIMINARY DATA SHEET
Figure 9. 2.5 Gb/s Output Data Eye Diagram
Mean `1' Level Trise, Tfall Vripple Trise, Tfall Vover 100%
80% Tpw Vmax Vmin Vmean Data Crossing Meas.
20%
0% Jpp Mean `0' Level
Tpw = Vmax = Vmin = Vmean = Trise = Tfall = %over = %under = %ripple = Jpp = half of input waveform period maximum peak-to-peak voltage minimum peak-to-peak voltage (eye interior) Mean peak-to-peak voltage (mean eye opening) 20% to 80% rise time, mean `0' to mean `1' 20% to 80% fall time, mean `0' to mean `1' Vover/Vmean X 100% Vunder/Vmean X 100% Vripple/Vmean X 100% peak-to-peak data crossing jitter Note: mimimum display persistence of 2 s is assmed for the above measurements.
Vripple
Jpp
Vunder
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TQ8213
PRELIMINARY DATA SHEET
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TELECOM PRODUCTS
SONET/SDH/ATM PRODUCTS
Figure 10. Typical 2.5 Gb/s Output Data Eye Scope Shot
TQ8213
PRELIMINARY DATA SHEET
Typical Application
Figure 8. TTL 16:1 Multiplexing Application with Internal PLL and VCO
+8.3V
VDRIVE 155.53Mb/s TTL Interface TD1(0)-TD1(7) TDPAR1 TD2(0)-TD2(7) TDPAR2 CK155 TDPERR VLEVEL
2.48832Gb/s
DOUT NDOUT
A.C. Terminated
E/O Module
Peak Detector
CLKIN
VSEN1
Ve
Variable Current Source
VDD
VOSC VTUNEIN VTUNEO
VSEN10
VSYMX LOCK REFCLK
38.88MHz +5.0V GND
VSYMX Control
CK39 VDD VEE
HCKOUT
2.5GHz clock monitor
System 38.88Mhz
CLKSEL MODE(1) MODE(0)
VEE (GND) N.C. VEE (GND)
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TQ8213
PRELIMINARY DATA SHEET
+8.3V
VDRIVE TD10-TD17 TDPAR1 TD20-TD27 TDPAR2 TD30-TD37 TDPAR3 TD40-TD47 TDPAR4 CK78 TDPERR CLKIN
2.48832Gb/s
77.76Mb/s TTL Interface
DOUT NDOUT
A.C. Terminated
E/O Module
Peak Detector
VLEVEL
VSEN1
Ve
Variable Current Source
VSEN10
VDD
VOSC VTUNEIN
e
38.88MHz
VSYMX
VSYMX Control
CK39
HCKOUT BRV
2.5GHz clock monitor
System 38.88Mhz
+5.0V GND
VDD VEE
CLKSEL MODE(1) MODE(0)
VEE (GND) VEE (GND) N.C.
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SONET/SDH/ATM PRODUCTS
Figure 9. 32:1 Multiplexing Application with External PLL and Internal VCO
TQ8213
PRELIMINARY DATA SHEET
Figrure 10. 208-pin BGA Mechanical Dimensions
Top view
D
Bottom view
D1
17 16 15 14 13 12 11 10 9 8 7 6 5432 1 A B C D E F G H J K L M N P R T U
A1 Ball Corner
A1 Ball I.D. Mark E E1 e
45o 0.5mm Chamfer
e
b
Note: Heat Spreader is at VDD volts.
A1
Side View Section
C
A
P aaa
Table 9. 208-pin BGA Dimensions
Symbol A A1 D D1 E E1 b c aaa e P Parameter Overall Thickness Ball Height Body Size Ball Footprint Body Size Ball Footprint Ball Diameter Body Thickness Seating Plane Clearance Ball Pitch Encapsulation Clearance 0.15 1.27 TYP. 0.65 0.85 22.80 Min 1.45 0.60 22.80 Nom 1.55 0.65 23.00 20.32 (BSC.) 23.00 20.32 (BSC.) 0.75 0.90 0.85 0.95 0.15 Max 1.65 0.70
23.20 23.20
Note: All dimensions in millimeters (mm)
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TQ8213
PRELIMINARY DATA SHEET
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. www.TriQuint.com Copyright (c) 1999 TriQuint Semiconductor, Inc. All rights reserved. Revision 0.3.A June 1999
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TELECOM PRODUCTS
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